1. Field of the Invention
The invention relates to a MOS semiconductor storage module with MOS transistor storage cells disposed between word and bit lines, in which a weighting network is disposed symmetrically in two bit lines, in each case, for evaluating the read signals appearing on the bit lines, in which the weighting networks are arranged in a column, and in which the storage cells connected to the bit lines leading to first inputs of the weighting networks form a first storage cell field and the storage cells connected to the bit lines leading to second inputs of the weighting networks form a second storage cell field.
2. Description of the Prior Art
It is know for MOS stores to be designed such that an MOS transistor storage cell is disposed at the intersections of word and bit lines. Such a transistor storage cell can be a known single transistor storage cell, for example. In order to be able to evaluate the read signals appearing on the bit lines during the reading operation, which signals are however very small, one weighting network is disposed symmetrically in two bit lines in each case. Such a weighting network can be constituted by a symmetrical flip-flop, for instance. Then such a MOS store is built on a storage module from a column of weighting networks and two storage cell fields of which a first is disposed on one side of the column of weighting networks and a second on the other side of the column of weighting networks. Such a MOS store can be found for example in the periodical Electronics, Sept. 13, 1973, pages 117 to 121.
Since the read signals are very small, it must be ensured that the storage cell fields are formed on both sides of the weighting networks as symmetrically as possible. Therefore, when selecting a storage cell during the reading operation the disturbances occurring in the process must be equal on both sides of the weighting network, identical increases in capacitance must take place on both sides and the bit lines must be charged to the same bias level before the reading operation. These requirements can be satisfied using the following measures: The bit lines are charged up by identical charging transistors that are actuated by an identical charging timing signal. The disturbances that arise through the selection of a cell column on one side of the weighting network are equalized by identical disturbances by selecting so-called compensation cells (dummy cells) on the other side. The capacitive equilibrium on both sides of the weighting network is also achieved with the aid of the compensation cells which balance the increase in capacitance on the bit lines through the called cells. In addition, the capacitive imbalance which arises as a result of selecting a selector switch disposed between a bit line and a date line is corrected by a special equlization element on the other bit line associated with the same weighting network.